The present invention relates to a semiconductor device, and more specifically, to a single poly-gate high-density multi-state mask ROM cells.
Recently, with the progress of semiconductor IC""s design and fabricating technology, the popular electronic merchandises, such as portable telecommunications, laptop computers, DSC (digital still camera), play-station II, PDA (personal digital assistant), MP3 player, all of them are with the characteristics of light, thin, short, and small. In such devices a very high-density non-volatile mask ROMs are demanded. To achieve very high-density mask ROM, a prior art is proposed by Bertagnoili et al., in the reference, xe2x80x9cB. Bertagnoili et al., xe2x80x98ROS: An Extremely High Density Mask ROM Technology Based On Vertical Transistor Cellsxe2x80x99, Symp. on VLSI Tech. Dig., p, 58, 1996.+ In the reference, the cells having a vertical MOS transistor in a trench which allows to use the bottom of the trench as additional self-aligned bit line, and thus to double the bit line density. The technology is enabling an approximately twofold packing density compared to conventional planar ROM.
However, for double or even multi-fold the storage capacities without increasing chip area, a mask ROM structure using a novel multi-state (xe2x89xa73 kinds of state) concept is a trend. For example, if memory cells store only data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d states, a more great number of mask ROM cell transistors should be demanded to provide storage data as compare with that of memory cells which can store four kinds of states, called multiple state mask ROM cells.
A conventional multi-value ROM stores with more than three states, in the manner that changes the threshold voltage of memory cell transistors is given by Sheng et al., in U.S. Pat. No. 5,585,297 issued on Dec. 17, 1996. In the method, a number of ion implantation stages using boron ions are performed incorporating with several mask patterns and different dosage level. The high dose boron coding implant will result in a lower junction breakdown performance of the coded MOSFET and a very high band-to band leakage current between the adjacent cells as is stated in the reference xe2x80x9cU.S. Pat. No. 5,683,925, to Irani et al., issued on Nov. 4, 1997.xe2x80x9d Hence, Irani et al., in their patent proposed a method of fabricating the mask ROM to solve above issues. In the method, a thick gate oxide layer 18 is thermally grown within ROM array area 30, even the gate oxide 2 in the periphery 32 is thinner, as shown in FIG. 1.
An alternative method is proposed by Takiziawa et al., in U.S. Pat. No. 5,556,800 issued on Sep. 17 (1996).xe2x80x9d Takiziawa et al., In the Takiziawa""s patent, the gate insulating layer""s thickness is varied to change the threshold voltage of channel region. The channel region is divided into dual parts; one divided part having a different gate oxide thickness from the other, and thus a different transitivity for ion implant. Namely, the gate electrode has different characteristics of a drain current corresponding to a gate voltage (IDxe2x88x92VG) in the channel regions adjacent to each other.
A recent U.S. Pat. No. 6,133,102 issued on Oct. 17, 2000 issued to Wu disclosed a recipe which combines the concepts of the double the bit line density and multi-state storage way to fabricate double poly- gate high density multi-state flat mask ROM cells on a silicon substrate.
An object of the present invention is to propose a simpler method than above prior art. In the method, only two oxide layer growth stages and twice ion implant incorporating with single-poly, and patterning steps are required to form such multi-state mask ROM cells.
An object of the present invention is provided a multi-state Mask ROM forming technique.
A method of forming multi-state mask ROM cells on a semiconductor substrate is disclosed. In the method, single polysilicon for word line and two ion-implant steps are required. One is for form buried bit lines and the other one is for forming coding regions. The ion implants associated with coding oxide can build up at least four states mask ROM. The method comprises following steps. Firstly, a pad oxide layer is formed on a semiconductor substrate. Then the pad oxide layer is patterned so as to form a plurality of first coding oxide regions. Thereafter, another photoresist pattern is formed to define buried bit line regions. A plurality of predetermined buried bit line regions are defined amid the first coding oxide regions. Then, a first ion implant by implanting n-type impurities into the semiconductor substrate using the photoresist pattern as a mask. After stripping the photoresist pattern, a first thermal oxidation is performed to grow oxide layer and driving the n-type impurities into the semiconductor substrate. Three types of oxide layer are formed with different thickness. Thereafter, a conductive layer are formed and then patterned as word lines. Subsequently, a photoresist pattern is formed to define second coding region. The openings of the photoresist pattern located at regions having either first coding oxide regions or the thinnest type oxide layer thereon. Finally, an ion implant using boron ion is performed. Accordingly four states mask ROM is formed.